The present invention relates to a decoder for decoding digital pulses, and reconfigurable circuit that includes a digital pulse decoder.
Semiconductor die packages are being manufactured with increased circuit functionality to package pin count (external terminal count). However, due to the limited number of external terminals or pins, the controllability and observablity of internal circuit nodes can often be inadequate unless testability is designed into the circuit.
Testability is designed into circuits by the use of dedicated test pins. These dedicated test pins are often used in structured Design For Testability (DFT) techniques such as Scan Path, Level Sensitive Scan Design (LSSD), Built In Self-Test (BIST) and Random Access Scan. However, because the number of external pins is limited, these dedicated test pins are provided at the cost of reduced functionality and normal run-time accessibility of functional modules of the circuit.